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| author | Liguros - Gitlab CI/CD [develop] <gitlab@liguros.net> | 2026-04-09 07:14:10 +0000 |
|---|---|---|
| committer | Liguros - Gitlab CI/CD [develop] <gitlab@liguros.net> | 2026-04-09 07:14:10 +0000 |
| commit | 9d2e1604c9c5507861156ab4013b33d24bafa01f (patch) | |
| tree | c8641d6d747739bfc5201496c03f2e7e4a502011 /dev-python/sip | |
| parent | a49b06a8e3f4f5acd879c26026dde277285ed03d (diff) | |
| download | srcux-9d2e1604c9c5507861156ab4013b33d24bafa01f.tar.gz srcux-9d2e1604c9c5507861156ab4013b33d24bafa01f.tar.xz srcux-9d2e1604c9c5507861156ab4013b33d24bafa01f.zip | |
Adding metadata
Diffstat (limited to 'dev-python/sip')
| -rw-r--r-- | dev-python/sip/sip-6.15.3.ebuild | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/dev-python/sip/sip-6.15.3.ebuild b/dev-python/sip/sip-6.15.3.ebuild index f355d5351183..7c88e3eb1b57 100644 --- a/dev-python/sip/sip-6.15.3.ebuild +++ b/dev-python/sip/sip-6.15.3.ebuild @@ -16,7 +16,7 @@ SRC_URI=" LICENSE="BSD-2 BSD" SLOT="5" -KEYWORDS="~alpha ~amd64 ~arm ~arm64 ~hppa ~loong ~ppc ~ppc64 ~riscv ~sparc ~x86" +KEYWORDS="~alpha amd64 arm arm64 ~hppa ~loong ppc ppc64 ~riscv ~sparc x86" RDEPEND=" dev-python/packaging[${PYTHON_USEDEP}] |